Platform-based IC (integrated circuit) design is a powerful concept for coping with the increased pressure on time-to-market, design and manufacturing costs encountered in the current IC market. A platform is a large-scale, high-complexity semiconductor device that includes one or more of the following elements: (1) memory; (2) a customizable array of transistors; (3) an IP (intellectual property) block; (4) a processor, e.g., an ESP (embedded standard product); (5) an embedded programmable logic block; and (6) interconnect. RapidChip™ developed by LSI Logic Corp. is an instance of a platform. The basic idea behind the platform-based design is to avoid designing and manufacturing a chip from scratch. Some portion of the chip's architecture is predefined for a specific type of application. Through extensive design reuse, the platform-based design may provide faster time-to-market and reduced design cost.
Under a platform approach, there are two distinct steps entailed in creating a final end-user product: a prefabrication step and a customization step. In a prefabrication step, a slice is built on a wafer. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the metal layers or top metal layers to be completed with the customer's unique IP. For example, RapidSlice™ developed by LSI Logic Corp. is an instance of a slice. One or more slices may be built on a single wafer. It is understood that a slice may include one or more bottom metal layers or may include no metal layers at all. In a preferred embodiment of the prefabrication step, portions of the metal layers are pre-specified to implement the pre-defined blocks of the platform and the diffusion processes are carried out in a wafer fab. The base characteristics, in terms of the IP, the processors, the memory, the interconnect, the programmable logic and the customizable transistor array, are all pre-placed in the design and pre-diffused in the slice. However, a slice is still fully decoupled because the customer has not yet introduced the function into the slice. In a customization step, the customer-designed function is merged with the pre-defined blocks and the metal layers (or late-metal components) are laid down, which couple the elements that make up the slice built in the wafer fab, and the customizable transistor array is configured and given its characteristic function. In other embodiments, early-metal steps may be part of the pre-fabricated slice to reduce the time and cost of the customization step, resulting in a platform which is more coupled and specific. It is understood that a prefabrication step and a customization step may be performed in different foundries. For example, a slice may be manufactured in one foundry. Later, in a customization step, the slice may be pulled from inventory and metalized, which gives the slice its final product characteristics in a different foundry.
Within the past several years, platforms have emerged as a viable alternative to cell-based ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Arrays). Platforms fit the gap for those designs where the resources and costs of a cell-based ASIC are not justified, nor the pricing or performance of an FPGA. The platform is intended to provided quicker time to market and lower initial costs of a cell-based ASIC, but at a performance and capability of the cell-based ASIC. On the other hand, FPGAs, although offering a quicker time to market at lower initial costs, become prohibitive at larger volumes or where ASIC like performance is needed. For example, a 130 nm platform offers better gate density and performance for a given square millimeter than a 90 nm FPGA.
One of the biggest challenges facing platforms is design fit. In comparing platforms to cell-based ASICs, much of the differences come from the base layers of the wafer which are fixed for platforms. For a given platform, the number of gates, the number of memory instances and bits, as well as specialized diffused IP (intellectual property), are pre-determined. The selection of the IP and the placement of the IP in the architecture of the platform will determine the success or fit of the platform to multiple customer requirements.
In addition, for the platform vendor, the challenge is to define a core platform architecture that is efficient and flexible, so that it can be maintained and leveraged across multiple platforms, to lower the inherent design and development costs of the platform family, and to provide a competitive advantage.
The conventional solution to defining platforms is to either maintain the same architecture currently supported by FPGAs which is memory centric or take an ASIC mentality that is gate centric. In the FPGA based architecture, the structure of the architecture is focused on memory placement and access, with gates added to support the memories. With an ASIC based platform approach, the focus is adding memories to support the gates, and is typically a point solution with specific requirements embedded to address specific applications (vs. a wide range of applications). Neither approach adequately or generically addresses the SerDes (Serializer/Deserializer) requirements with respect to high end platforms.
Thus, it is desirable to provide an architecture and method for a platform which may address the SerDes requirements.